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Quartz64 - Kühler

Verschoben Quartz64 - A
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  • Im Moment aktuell noch überhaupt nicht nötig aber wollte es trotzdem hier mal vorstellen.

    20210722_101305.jpg

    Auf dieses Board und auch genauso auf den ROCKPro64 passen ganz normale NorthBridge Kühler. Hier bei diesem Modell könnte man noch einen Lüfter drauf schrauben. Da ich keine Lüfter mag, mein NAS auf ROCKPro64 Basis hat auch nur einen Kühlkörper drauf, kommt da auch nie einer drauf.

  • Im Moment aktuell noch überhaupt nicht nötig aber wollte es trotzdem hier mal vorstellen.

    20210722_101305.jpg

    Auf dieses Board und auch genauso auf den ROCKPro64 passen ganz normale NorthBridge Kühler. Hier bei diesem Modell könnte man noch einen Lüfter drauf schrauben. Da ich keine Lüfter mag, mein NAS auf ROCKPro64 Basis hat auch nur einen Kühlkörper drauf, kommt da auch nie einer drauf.

    @frankm

    the ram chip is higher as the cpu 😉

  • @frankm

    the ram chip is higher as the cpu 😉

    @thc013 I use an thermal pad. So i think it isn't an problem.

  • FrankMF FrankM verschob dieses Thema von Hardware am
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  • [V] Quartz64B V1.3

    Frank's Resterampe quartz64 verkauf
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  • Quartz64 - SPDIF Modul

    Verschoben Quartz64 - A quartz64 linux
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    FrankMF
    Für das bequeme Umschalten der Soundkarten kann man das Tool alsamixer benutzen. pacman -S alsa-utils Danach alsamixer [image: 1633791802992-e912744f-8f69-4b28-a50b-7ffc8a3ab399-grafik.png]
  • Quartz64 - SPI

    Verschoben Quartz64 - A quartz64 pine64
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    FrankMF
    Bitte unbedingt beachten! https://forum.frank-mankel.org/topic/1042/quartz64-missing-spi
  • Ubuntu Bionic - Namen der Interfaces umstellen

    ROCKPro64 howto rockpro64
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  • Eure Meinung zum ROCKPro64 ?

    ROCKPro64 rockpro64
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  • RockPro64 - Firewall mit zwei LAN Schnittstellen!

    Verschoben ROCKPro64 howto rockpro64
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  • 0 Stimmen
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    FrankMF
    Ergänzung Eine andere SATA-Karte und eine Riser-Karte mit angeschlossener GPU startet nicht. rock64@rockpro64v2_1:~$ uname -a Linux rockpro64v2_1 4.4.132-1075-rockchip-ayufan-ga83beded8524 #1 SMP Thu Jul 26 08:22:22 UTC 2018 aarch64 aarch64 aarch64 GNU/Linux
  • stretch-minimal-rockpro64

    Verschoben Linux rockpro64
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    FrankMF
    Mal ein Test was der Speicher so kann. rock64@rockpro64:~/tinymembench$ ./tinymembench tinymembench v0.4.9 (simple benchmark for memory throughput and latency) ========================================================================== == Memory bandwidth tests == == == == Note 1: 1MB = 1000000 bytes == == Note 2: Results for 'copy' tests show how many bytes can be == == copied per second (adding together read and writen == == bytes would have provided twice higher numbers) == == Note 3: 2-pass copy means that we are using a small temporary buffer == == to first fetch data into it, and only then write it to the == == destination (source -> L1 cache, L1 cache -> destination) == == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == == brackets == ========================================================================== C copy backwards : 2812.7 MB/s C copy backwards (32 byte blocks) : 2811.9 MB/s C copy backwards (64 byte blocks) : 2632.8 MB/s C copy : 2667.2 MB/s C copy prefetched (32 bytes step) : 2633.5 MB/s C copy prefetched (64 bytes step) : 2640.8 MB/s C 2-pass copy : 2509.8 MB/s C 2-pass copy prefetched (32 bytes step) : 2431.6 MB/s C 2-pass copy prefetched (64 bytes step) : 2424.1 MB/s C fill : 4887.7 MB/s (0.5%) C fill (shuffle within 16 byte blocks) : 4883.0 MB/s C fill (shuffle within 32 byte blocks) : 4889.3 MB/s C fill (shuffle within 64 byte blocks) : 4889.2 MB/s --- standard memcpy : 2807.3 MB/s standard memset : 4890.4 MB/s (0.3%) --- NEON LDP/STP copy : 2803.7 MB/s NEON LDP/STP copy pldl2strm (32 bytes step) : 2802.1 MB/s NEON LDP/STP copy pldl2strm (64 bytes step) : 2800.7 MB/s NEON LDP/STP copy pldl1keep (32 bytes step) : 2745.5 MB/s NEON LDP/STP copy pldl1keep (64 bytes step) : 2745.8 MB/s NEON LD1/ST1 copy : 2801.9 MB/s NEON STP fill : 4888.9 MB/s (0.3%) NEON STNP fill : 4850.1 MB/s ARM LDP/STP copy : 2803.8 MB/s ARM STP fill : 4893.0 MB/s (0.5%) ARM STNP fill : 4851.7 MB/s ========================================================================== == Framebuffer read tests. == == == == Many ARM devices use a part of the system memory as the framebuffer, == == typically mapped as uncached but with write-combining enabled. == == Writes to such framebuffers are quite fast, but reads are much == == slower and very sensitive to the alignment and the selection of == == CPU instructions which are used for accessing memory. == == == == Many x86 systems allocate the framebuffer in the GPU memory, == == accessible for the CPU via a relatively slow PCI-E bus. Moreover, == == PCI-E is asymmetric and handles reads a lot worse than writes. == == == == If uncached framebuffer reads are reasonably fast (at least 100 MB/s == == or preferably >300 MB/s), then using the shadow framebuffer layer == == is not necessary in Xorg DDX drivers, resulting in a nice overall == == performance improvement. For example, the xf86-video-fbturbo DDX == == uses this trick. == ========================================================================== NEON LDP/STP copy (from framebuffer) : 602.5 MB/s NEON LDP/STP 2-pass copy (from framebuffer) : 551.6 MB/s NEON LD1/ST1 copy (from framebuffer) : 667.1 MB/s NEON LD1/ST1 2-pass copy (from framebuffer) : 605.6 MB/s ARM LDP/STP copy (from framebuffer) : 445.3 MB/s ARM LDP/STP 2-pass copy (from framebuffer) : 428.8 MB/s ========================================================================== == Memory latency test == == == == Average time is measured for random memory accesses in the buffers == == of different sizes. The larger is the buffer, the more significant == == are relative contributions of TLB, L1/L2 cache misses and SDRAM == == accesses. For extremely large buffer sizes we are expecting to see == == page table walk with several requests to SDRAM for almost every == == memory access (though 64MiB is not nearly large enough to experience == == this effect to its fullest). == == == == Note 1: All the numbers are representing extra time, which needs to == == be added to L1 cache latency. The cycle timings for L1 cache == == latency can be usually found in the processor documentation. == == Note 2: Dual random read means that we are simultaneously performing == == two independent memory accesses at a time. In the case if == == the memory subsystem can't handle multiple outstanding == == requests, dual random read has the same timings as two == == single reads performed one after another. == ========================================================================== block size : single random read / dual random read 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.0 ns / 0.0 ns 65536 : 4.5 ns / 7.2 ns 131072 : 6.8 ns / 9.7 ns 262144 : 9.8 ns / 12.8 ns 524288 : 11.4 ns / 14.7 ns 1048576 : 16.0 ns / 22.6 ns 2097152 : 114.0 ns / 175.3 ns 4194304 : 161.7 ns / 219.9 ns 8388608 : 190.7 ns / 241.5 ns 16777216 : 205.3 ns / 250.5 ns 33554432 : 212.9 ns / 255.5 ns 67108864 : 222.3 ns / 271.1 ns