kann ich so unterschreiben deine aussagen 😄
AtomicPi - CPU- / Speichertest
-
Mal schauen was wir so für's Geld bekommen
Wer Vergleichswerte zum ROCKPro64 braucht -> https://forum.frank-mankel.org/topic/80/benchmarks/5
Verbauter Speicher im Atomic Pi
- 2GB DDR3L-1600
zum Vergleich im ROCKPro64
- 2GB LPDDR4
Software
Das System was ich hier teste ist ein Ubuntu mit LXDE Oberfläche.
Welcome to Ubuntu 18.04.2 LTS (GNU/Linux 4.15.18-dli x86_64) Linux localhost 4.15.18-dli #1 SMP Fri Feb 22 15:10:35 UTC 2019 x86_64 x86_64 x86_64 GNU/LinuxCPU
atomicpi@localhost:~$ sysbench --test=cpu --cpu-max-prime=20000 run WARNING: the --test option is deprecated. You can pass a script name or path on the command line without any options. sysbench 1.0.11 (using system LuaJIT 2.1.0-beta3) Running the test with following options: Number of threads: 1 Initializing random number generator from current time Prime numbers limit: 20000 Initializing worker threads... Threads started! CPU speed: events per second: 142.17 General statistics: total time: 10.0063s total number of events: 1423 Latency (ms): min: 6.91 avg: 7.03 max: 10.90 95th percentile: 7.84 sum: 10003.64 Threads fairness: events (avg/stddev): 1423.0000/0.00 execution time (avg/stddev): 10.0036/0.00Speicher
atomicpi@localhost:~$ cryptsetup benchmark # Tests are approximate using memory only (no storage IO). PBKDF2-sha1 264791 iterations per second for 256-bit key PBKDF2-sha256 344020 iterations per second for 256-bit key PBKDF2-sha512 209046 iterations per second for 256-bit key PBKDF2-ripemd160 211406 iterations per second for 256-bit key PBKDF2-whirlpool 160824 iterations per second for 256-bit key argon2i 4 iterations, 377254 memory, 4 parallel threads (CPUs) for 256-bit key (requested 2000 ms time) argon2id 4 iterations, 372352 memory, 4 parallel threads (CPUs) for 256-bit key (requested 2000 ms time) # Algorithm | Key | Encryption | Decryption aes-cbc 128b 214.5 MiB/s 313.4 MiB/s serpent-cbc 128b 22.7 MiB/s 70.3 MiB/s twofish-cbc 128b 56.3 MiB/s 64.1 MiB/s aes-cbc 256b 171.7 MiB/s 244.4 MiB/s serpent-cbc 256b 27.3 MiB/s 70.4 MiB/s twofish-cbc 256b 64.7 MiB/s 64.1 MiB/s aes-xts 256b 250.9 MiB/s 255.8 MiB/s serpent-xts 256b 67.1 MiB/s 67.8 MiB/s twofish-xts 256b 61.4 MiB/s 61.2 MiB/s aes-xts 512b 207.5 MiB/s 209.1 MiB/s serpent-xts 512b 68.3 MiB/s 67.8 MiB/s twofish-xts 512b 61.3 MiB/s 61.1 MiB/sUnd noch ein Test
atomicpi@localhost:~/tinymembench$ ./tinymembench tinymembench v0.4.9 (simple benchmark for memory throughput and latency) ========================================================================== == Memory bandwidth tests == == == == Note 1: 1MB = 1000000 bytes == == Note 2: Results for 'copy' tests show how many bytes can be == == copied per second (adding together read and writen == == bytes would have provided twice higher numbers) == == Note 3: 2-pass copy means that we are using a small temporary buffer == == to first fetch data into it, and only then write it to the == == destination (source -> L1 cache, L1 cache -> destination) == == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == == brackets == ========================================================================== C copy backwards : 1848.7 MB/s C copy backwards (32 byte blocks) : 1849.6 MB/s C copy backwards (64 byte blocks) : 1849.3 MB/s C copy : 1855.4 MB/s C copy prefetched (32 bytes step) : 1658.4 MB/s C copy prefetched (64 bytes step) : 1662.2 MB/s C 2-pass copy : 1648.0 MB/s C 2-pass copy prefetched (32 bytes step) : 1323.2 MB/s C 2-pass copy prefetched (64 bytes step) : 1320.0 MB/s C fill : 2914.0 MB/s C fill (shuffle within 16 byte blocks) : 2913.6 MB/s C fill (shuffle within 32 byte blocks) : 2913.5 MB/s C fill (shuffle within 64 byte blocks) : 2913.5 MB/s --- standard memcpy : 2709.4 MB/s (1.3%) standard memset : 2951.1 MB/s (0.5%) --- MOVSB copy : 1737.5 MB/s MOVSD copy : 1737.7 MB/s (0.2%) SSE2 copy : 1823.7 MB/s SSE2 nontemporal copy : 2547.6 MB/s SSE2 copy prefetched (32 bytes step) : 1836.6 MB/s SSE2 copy prefetched (64 bytes step) : 1837.3 MB/s SSE2 nontemporal copy prefetched (32 bytes step) : 1898.4 MB/s (0.5%) SSE2 nontemporal copy prefetched (64 bytes step) : 1928.1 MB/s (0.4%) SSE2 2-pass copy : 1766.7 MB/s SSE2 2-pass copy prefetched (32 bytes step) : 1497.6 MB/s SSE2 2-pass copy prefetched (64 bytes step) : 1509.4 MB/s SSE2 2-pass nontemporal copy : 1160.6 MB/s SSE2 fill : 2948.8 MB/s SSE2 nontemporal fill : 4284.4 MB/s (0.3%) ========================================================================== == Framebuffer read tests. == == == == Many ARM devices use a part of the system memory as the framebuffer, == == typically mapped as uncached but with write-combining enabled. == == Writes to such framebuffers are quite fast, but reads are much == == slower and very sensitive to the alignment and the selection of == == CPU instructions which are used for accessing memory. == == == == Many x86 systems allocate the framebuffer in the GPU memory, == == accessible for the CPU via a relatively slow PCI-E bus. Moreover, == == PCI-E is asymmetric and handles reads a lot worse than writes. == == == == If uncached framebuffer reads are reasonably fast (at least 100 MB/s == == or preferably >300 MB/s), then using the shadow framebuffer layer == == is not necessary in Xorg DDX drivers, resulting in a nice overall == == performance improvement. For example, the xf86-video-fbturbo DDX == == uses this trick. == ========================================================================== MOVSD copy (from framebuffer) : 34.4 MB/s (0.3%) MOVSD 2-pass copy (from framebuffer) : 33.8 MB/s SSE2 copy (from framebuffer) : 34.5 MB/s SSE2 2-pass copy (from framebuffer) : 33.9 MB/s ========================================================================== == Memory latency test == == == == Average time is measured for random memory accesses in the buffers == == of different sizes. The larger is the buffer, the more significant == == are relative contributions of TLB, L1/L2 cache misses and SDRAM == == accesses. For extremely large buffer sizes we are expecting to see == == page table walk with several requests to SDRAM for almost every == == memory access (though 64MiB is not nearly large enough to experience == == this effect to its fullest). == == == == Note 1: All the numbers are representing extra time, which needs to == == be added to L1 cache latency. The cycle timings for L1 cache == == latency can be usually found in the processor documentation. == == Note 2: Dual random read means that we are simultaneously performing == == two independent memory accesses at a time. In the case if == == the memory subsystem can't handle multiple outstanding == == requests, dual random read has the same timings as two == == single reads performed one after another. == ========================================================================== block size : single random read / dual random read, [MADV_NOHUGEPAGE] 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 1.8 ns / 3.3 ns 65536 : 4.5 ns / 7.4 ns 131072 : 5.8 ns / 9.2 ns 262144 : 8.6 ns / 12.7 ns 524288 : 10.6 ns / 15.3 ns 1048576 : 12.5 ns / 18.1 ns 2097152 : 82.6 ns / 126.2 ns 4194304 : 117.9 ns / 161.6 ns 8388608 : 136.9 ns / 177.7 ns 16777216 : 146.9 ns / 186.7 ns 33554432 : 153.0 ns / 193.4 ns 67108864 : 171.9 ns / 221.6 ns block size : single random read / dual random read, [MADV_HUGEPAGE] 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 1.8 ns / 3.3 ns 65536 : 4.5 ns / 7.4 ns 131072 : 5.8 ns / 9.2 ns 262144 : 8.6 ns / 12.7 ns 524288 : 10.0 ns / 14.5 ns 1048576 : 12.1 ns / 17.4 ns 2097152 : 76.1 ns / 117.1 ns 4194304 : 107.5 ns / 147.0 ns 8388608 : 123.0 ns / 156.9 ns 16777216 : 130.7 ns / 160.6 ns 33554432 : 134.8 ns / 162.5 ns 67108864 : 153.1 ns / 185.4 nsFazit
Der Speicher ist deutlich langsamer als beim ROCKPro64, war zu erwarten. Ich kann aber alle beruhigen, das fühlt sich auf dem Desktop recht gut an. Habe bei dieser Preisklasse eher nicht damit gerechnet, das der Desktop überhaupt vernünftig läuft. Aber, die ersten Minuten des Testens, es ist gut nutzbar. Wenn, wie nicht anders zu erwarten, das ein oder andere nicht funktioniert.
- Soundausgabe
-
Info's zur CPU
Seite von Intel zur CPU https://ark.intel.com/content/www/de/de/ark/products/93361/intel-atom-x5-z8350-processor-2m-cache-up-to-1-92-ghz.html
cpuid
atomicpi@atomicpi:~$ cpuid CPU 0: vendor_id = "GenuineIntel" version information (1/eax): processor type = primary processor (0) family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6) model = 0xc (12) stepping id = 0x4 (4) extended family = 0x0 (0) extended model = 0x4 (4) (simple synth) = Intel Pentium N3000 / Celeron N3000 (Braswell), 14nm miscellaneous (1/ebx): process local APIC physical ID = 0x0 (0) cpu count = 0x10 (16) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true VME: virtual-8086 mode enhancement = true DE: debugging extensions = true PSE: page size extensions = true TSC: time stamp counter = true RDMSR and WRMSR support = true PAE: physical address extensions = true MCE: machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true MTRR: memory type range registers = true PTE global bit = true MCA: machine check architecture = true CMOV: conditional move/compare instr = true PAT: page attribute table = true PSE-36: page size extension = true PSN: processor serial number = false CLFLUSH instruction = true DS: debug store = true ACPI: thermal monitor and clock ctrl = true MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true SS: self snoop = true hyper-threading / multi-core supported = true TM: therm. monitor = true IA64 = false PBE: pending break event = true feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true DTES64: 64-bit debug store = true MONITOR/MWAIT = true CPL-qualified debug store = true VMX: virtual machine extensions = true SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = true TM2: thermal monitor 2 = true SSSE3 extensions = true context ID: adaptive or shared L1 data = false SDBG: IA32_DEBUG_INTERFACE = false FMA instruction = false CMPXCHG16B instruction = true xTPR disable = true PDCM: perfmon and debug = true PCID: process context identifiers = false DCA: direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true x2APIC: extended xAPIC support = false MOVBE instruction = true POPCNT instruction = true time stamp counter deadline = true AES instruction = true XSAVE/XSTOR states = false OS-enabled XSAVE/XSTOR = false AVX: advanced vector extensions = false F16C half-precision convert instruction = false RDRAND instruction = true hypervisor guest status = false cache and TLB information (2): 0xa0: data TLB: 4K pages, fully, 32 entries 0xb4: data TLB: 4K pages, 4-way, 256 entries 0x61: instruction TLB: 4K pages, 48 entries 0xc2: data TLB: 4K & 2M pages, 4-way, 16 entries 0xff: cache data is in CPUID leaf 4 processor serial number: 0004-06C4-0000-0000-0000-0000 deterministic cache parameters (4): --- cache 0 --- cache type = data cache (1) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x7 (7) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x5 (5) number of sets - 1 = 0x3f (63) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 1 --- cache type = instruction cache (2) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x7 (7) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) number of sets - 1 = 0x3f (63) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 2 --- cache type = unified cache (3) cache level = 0x2 (2) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x3 (3) extra processor cores on this die = 0x7 (7) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) number of sets - 1 = 0x3ff (1023) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 1023 MONITOR/MWAIT (5): smallest monitor-line size (bytes) = 0x40 (64) largest monitor-line size (bytes) = 0x40 (64) enum of Monitor-MWAIT exts supported = true supports intrs as break-event for MWAIT = true number of C0 sub C-states using MWAIT = 0x0 (0) number of C1 sub C-states using MWAIT = 0x2 (2) number of C2 sub C-states using MWAIT = 0x0 (0) number of C3 sub C-states using MWAIT = 0x0 (0) number of C4 sub C-states using MWAIT = 0x0 (0) number of C5 sub C-states using MWAIT = 0x0 (0) number of C6 sub C-states using MWAIT = 0x3 (3) number of C7 sub C-states using MWAIT = 0x3 (3) Thermal and Power Management Features (6): digital thermometer = true Intel Turbo Boost Technology = true ARAT always running APIC timer = true PLN power limit notification = false ECMD extended clock modulation duty = false PTM package thermal management = false HWP base registers = false HWP notification = false HWP activity window = false HWP energy performance preference = false HWP package level request = false HDC base registers = false Intel Turbo Boost Max Technology 3.0 = false HWP capabilities = false HWP PECI override = false flexible HWP = false IA32_HWP_REQUEST MSR fast access mode = false ignoring idle logical processor HWP req = false digital thermometer thresholds = 0x2 (2) hardware coordination feedback = true ACNT2 available = false performance-energy bias capability = true extended feature flags (7): FSGSBASE instructions = false IA32_TSC_ADJUST MSR supported = true SGX: Software Guard Extensions supported = false BMI1 instructions = false HLE hardware lock elision = false AVX2: advanced vector extensions 2 = false FDP_EXCPTN_ONLY = false SMEP supervisor mode exec protection = true BMI2 instructions = false enhanced REP MOVSB/STOSB = true INVPCID instruction = false RTM: restricted transactional memory = false RDT-M: Intel RDT monitoring = false deprecated FPU CS/DS = true MPX: intel memory protection extensions = false RDT-A: Intel RDT allocation = false AVX512F: AVX-512 foundation instructions = false AVX512DQ: double & quadword instructions = false RDSEED instruction = false ADX instructions = false SMAP: supervisor mode access prevention = false AVX512IFMA: fused multiply add = false PCOMMIT instruction = false CLFLUSHOPT instruction = false CLWB instruction = false Intel processor trace = false AVX512PF: prefetch instructions = false AVX512ER: exponent & reciprocal instrs = false AVX512CD: conflict detection instrs = false SHA instructions = false AVX512BW: byte & word instructions = false AVX512VL: vector length = false PREFETCHWT1 = false AVX512VBMI: vector byte manipulation = false UMIP: user-mode instruction prevention = false PKU protection keys for user-mode = false OSPKE CR4.PKE and RDPKRU/WRPKRU = false WAITPKG instructions = false AVX512_VBMI2 = false CET_SS: CET shadow stack = false GFNI: Galois Field New Instructions = false VAES instructions = false VPCLMULQDQ instruction = false AVX512_VNNI = false AVX512_BITALG: bit count/shiffle = false AVX512: VPOPCNTDQ instruction = false 5-level paging = false BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) RDPID: read processor D supported = false CLDEMOTE supports cache line demote = false MOVDIRI instruction = false MOVDIR64B intruction = false SGX_LC: SGX launch config supported = false AVX512_4VNNIW: neural network instrs = false AVX512_4FMAPS: multiply acc single prec = false fast short REP MOV = false PCONFIG = false CET_IBT: CET indirect branch tracking = false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa/eax): version ID = 0x3 (3) number of counters per logical processor = 0x2 (2) bit width of counter = 0x28 (40) length of EBX bit vector = 0x7 (7) Architecture Performance Monitoring Features (0xa/ebx): core cycle event not available = false instruction retired event not available = false reference cycles event not available = false last-level cache ref event not available = false last-level cache miss event not avail = false branch inst retired event not available = false branch mispred retired event not avail = false Architecture Performance Monitoring Features (0xa/edx): number of fixed counters = 0x3 (3) bit width of fixed counters = 0x28 (40) anythread deprecation = false x2APIC features / processor topology (0xb): --- level 0 (thread) --- bits to shift APIC ID to get next = 0x1 (1) logical processors at this level = 0x1 (1) level number = 0x0 (0) level type = thread (1) extended APIC ID = 0 --- level 1 (core) --- bits to shift APIC ID to get next = 0x4 (4) logical processors at this level = 0x4 (4) level number = 0x1 (1) level type = core (2) extended APIC ID = 0 extended feature flags (0x80000001/edx): SYSCALL and SYSRET instructions = true execution disable = true 1-GB large page support = false RDTSCP = true 64-bit extensions technology available = true Intel feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true LZCNT advanced bit manipulation = false 3DNow! PREFETCH/PREFETCHW instructions = true brand = " Intel(R) Atom(TM) x5-Z8350 CPU @ 1.44GHz" L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0x0 (0) instruction associativity = 0x0 (0) data # entries = 0x0 (0) data associativity = 0x0 (0) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0x0 (0) instruction associativity = 0x0 (0) data # entries = 0x0 (0) data associativity = 0x0 (0) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = 0x0 (0) size (KB) = 0x0 (0) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = 0x0 (0) size (KB) = 0x0 (0) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x0 (0) associativity = 16-way (8) size (KB) = 0x400 (1024) L3 cache information (0x80000006/edx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = L2 off (0) size (in 512KB units) = 0x0 (0) RAS Capability (0x80000007/ebx): MCA overflow recovery support = false SUCCOR support = false HWA: hardware assert support = false scalable MCA support = false Advanced Power Management Features (0x80000007/ecx): CmpUnitPwrSampleTimeRatio = 0x0 (0) Advanced Power Management Features (0x80000007/edx): TS: temperature sensing diode = false FID: frequency ID control = false VID: voltage ID control = false TTP: thermal trip = false TM: thermal monitor = false STC: software thermal control = false 100 MHz multiplier control = false hardware P-State control = false TscInvariant = true CPB: core performance boost = false read-only effective frequency interface = false processor feedback interface = false APM power reporting = false connected standby = false RAPL: running average power limit = false Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x24 (36) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Extended Feature Extensions ID (0x80000008/ebx): CLZERO instruction = false instructions retired count support = false always save/restore error pointers = false Logical CPU cores (0x80000008/ecx): number of CPU cores - 1 = 0x0 (0) ApicIdCoreIdSize = 0x0 (0) (multi-processing synth): multi-core (c=4) (multi-processing method): Intel leaf 0xb (APIC widths synth): CORE_width=4 SMT_width=1 (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0 (synth) = Intel Pentium N3000 / Celeron N3000 (Braswell), 14nmHier hat mich ganz besonders diese Zeile hier interessiert.
AES instruction = trueinxi -C
atomicpi@atomicpi:~$ inxi -C CPU: Topology: Quad Core model: Intel Atom x5-Z8350 bits: 64 type: MCP L2 cache: 1024 KiB Speed: 480 MHz min/max: 480/1920 MHz Core speeds (MHz): 1: 480 2: 480 3: 480 4: 480lscpu
atomicpi@atomicpi:~$ lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian Address sizes: 36 bits physical, 48 bits virtual CPU(s): 4 On-line CPU(s) list: 0-3 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 NUMA node(s): 1 Vendor ID: GenuineIntel CPU family: 6 Model: 76 Model name: Intel(R) Atom(TM) x5-Z8350 CPU @ 1.44GHz Stepping: 4 CPU MHz: 541.886 CPU max MHz: 1920.0000 CPU min MHz: 480.0000 BogoMIPS: 2880.00 Virtualization: VT-x L1d cache: 24K L1i cache: 32K L2 cache: 1024K NUMA node0 CPU(s): 0-3 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology tsc_reliable nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch epb pti tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms dtherm ida arat -
Ich hab vor paar Tagen ein Atomic Pi Ergebnis (der zweite x5-Z8350-Eintrag) zur sbc-bench-Liste hinzugefügt: https://github.com/ThomasKaiser/sbc-bench/blob/master/Results.md
CPU ist übrigens auf 1680MHz limitiert (UEFI/BIOS).
-
-
-
-
-
-
AtomicPi - Images - Allgemeine Info's
Angeheftet Images -
-