There's no way politicians will let one of the most important chip manufacturers die. If push comes to shove, they'll get subsidies

Yes, but RISC knows the exact position of that instruction in cache and how many instructions fit the instructions cache or pipeline. Like you said, it doesn't help with data cache.

Okay celebrating shareholder value I get in an indoctrinated pure* capitalist society.

But praising a monopoly? Wasn't that one of the main points capitalism should prevent?

The free market brings about competitors when they are needed.

Which does not hold true in reality due to various reasons and dynamics like entry cost...

Edit: These two are related as monopoly -> big shareholder value. Still the free market should prevent monopolies. Sooo Ahhh.

There's no way politicians will let one of the most important chip manufacturers die. If push comes to shove, they'll get subsidies

Trump's 100% tariffs on chips made outside the USA is puzzling. It it an attempt to force Intel, who do make chips in the USA, to become more competitive just through bullying everyone? Or does he know it will just cause more trouble and is he trying to drive Intel into the ground for revenge because they took Biden's money? Why is he also demanding that Intel's CEO resign? Does none of it make sense because Trump is a crazy old narcissist who has lost touch with reality and is now losing his mind?

Sure, but in the meantime I need to work with what I have... which is Intel (on some machines, at least).

From what I remember one of problems with CISC is that it has variable length instructions and these are harder to predict since you have to analyze all instructions up to the current one wheres for RISC you exactly know where is each instruction in memory/cache.

Coretemp and Ethernet. Also a few years ago the guy that maintained meshcentral (the only reason to pay extra $$$ for having Intel vPro compatibile computers in the workspace)

Basically this tells their biggest customers "next server needs to be based on AMD epyc"

How much money they could possibly "save" with those THREE salaries? Just cut one week of travel with private jet for the C class and the same savings are served

one of problems with CISC is that it has variable length instructions

RISC systems also have variable length instructions, they're just a bit stricter with the implementation that alleviates a lot of the issues (ARM instructions are always either 16-bits or 32-bits, while RISC-V is always a multiple of 16-bits and self-describing, similar to UTF-8)

Edit: Oh, and ARM further restricts instruction length based on a CPU flag, so you can't mix and match at an instruction level. It's always one or the other, or it's invalid.

Are you sure there's a significant difference in machine code between RISC and CISC after instructions are decoded?

The assembly in RISC is just an abstraction of the machine code, as it also is in CISC. If the underlying CPU has the same capabilities then it doesn't really matter what the assembly looks like?

Of course, the underlying CPUs aren't the same and that's the real point of differentiation.

I was thinking about Apple's M CPUs that have fixed length and they benefit out of it. It was explained on Anandtech years ago, here is a brief paragraph on the topic. Sadly Anandtech article(s) isn't available anymore.

Since this type of chip has a fixed instruction length, it becomes simple to load a large number of instructions and explore opportunities to execute operations in parallel. This is what’s called out-of-order execution, as explained by Anandtech in a highly technical analysis of the M1. Since complex CISC instructions can access memory before completing an operation, executing instructions in parallel becomes more difficult in contrast to the simpler RISC instructions.